All notable changes to this project will be documented in this file.


  • xlx_delay memory bug fix
  • x2730 online compile
  • updated user guide for Charge integration and patter generation
  • reset and clock signal type to std_logic_vector for legacy charge integrator
  • removed offline compile file for CAEN boards
  • fixed bug position for peak finder
  • SciSDK 1.2.58 with fixed caen


  • Fixed cup generator


  • Support to 10Gbps UDP on v27xx digitizer


  • Fixed incorrect management of extra license plugins/boards


  • Fixed missing welcome page


  • Fixed mixed file in the setup


  • Hide unlicensed plugins and boards


  • Fixed bug on autosize of subpage memory area < 512 bytes


  • Custom Packet for V2495
  • Max delay of software GD can be selected at compile time


  • Menu on right click of the three and double click to open page.
  • Fixed point constant component
  • Added new IIR Butterworth, Bessel, Chebyshev I, Chebyshev II, Elliptic, Notch and Resonant second order filter
  • Added new IIR Butterworth and Bessel first order IIR filter
  • Added new IIR first and Second order IIR filters using scattered look-ahead tecnique
  • Fixed rate meter memory region area
  • New hierarchical RegisterFile Json (for future version of SciSDK)
  • Readout element inside subpage (MR !18)
  • Magic Number in JSON RegisterFile to identify the firmware


  • ESS upgraded framework


  • Vivado cpu usage calculated in function of the number of core available. 4 up to 4 core, N-2 for more than 4 core
  • DMA working on all family x5560x
  • FLags lines are now available on R5560SE
  • Fixed bug MAGIC not written in in json file


  • Add 32 bit word size to list
  • Fixed x2730 x2740 library bug prevent access address > 0xffff


  • Fixed bug list on V2495
  • Fixed bug remote compilation with HLS on X27XX
  • Fixed bug on DPP list wave input when input is not connected
  • Updated CAENFee Libs
  • Updated V2495 old examples
  • Fixed bug on HW Gate and Delay on V2495
  • Fixed bug on create constant (size was always 8 bit)
  • Fixed bug on ALT+R Shortcut
  • New examples for DT5771 and V2730


  • Fixed bug crash software when create example
  • Fixed old V2495 old example (SciCompiler 2018)
  • Fixed bug crash software open some old project
  • Fixed missing ip core NIDNA in R5560-Minimal image
  • Fixed all bug in CustomHLD (missing TM, typo in template)
  • In CustomHDL automatic replace template name with module name. Just leave and save
  • Fixed bug in converting hex number in integer constant
  • Add code examples using Time Multiplexer for x2730
  • Fixed alt_list missing generic port
  • Fixed ALT+R Shortcut bug
  • Fixed bug setting wrong size in constant created from right click in-place menu
  • Add full MCA with QDC, PHA, PSD, CFD, ToF, timetag example for DT5771


  • Fixed files framework for offline compilation of x2730
  • Buf fix on histeresys of ToT
  • Display and key support for DT5771


  • Add support to V2730 (MR !17)
  • Updated DT555X library
  • GlobalClock to DT5571 framework
  • PSD enable property fix bug


  • Patch Vivado < 2022 with Y2K patch


  • Install report tool in Vivado


  • Official support for DT5771 (MR !16)


  • Missing block diagram file for offline and online compiler patched
  • Min/Max block bug corrected
  • Unconnected pin in subdesign bug corrected
  • Code factoring (MR !15)


  • All register can be read and write, include register file
  • Register write only (as well as mmc endpoint internal register) now can be also read (MR !14)


  • Support to HLS cores (this will allows to implement several new fetures and cores in next editions)
  • Support to DT5771
  • Removed autosave feature
  • Fixed visibility of board compatible toolbox elements managing the board restrictions
  • New organization of toolbar elements
  • Improved Charge Integration and PSD
  • Improved Trapezoidal PHA chain
  • Measure of rise time example
  • New oscilloscope component with gated average decimation
  • New oscilloscope component dual with gated average decimation
  • New oscilloscope component with 16/24/28 input width support
  • Fixed resource explorer to display chart in samples and not in incoerent time
  • Fixed resource explorer to display the decimation factor in absolute number
  • Fixed SciCompiler bug make it crash without internet connection
  • Fixed resource explorer to display signed number in oscilloscope


  • Ask to save on exit


  • Hidden I/O not compatible with the selected board. Applied to toolbar and quick menu


  • Bug fixed on register compiling. During save, register addresses were reset to 0.
  • Rise time of a signal measurament using R5560 (example)


  • Bug in log4net resource explorer


  • Better log on License Manager
  • R5560-A dcp missing


  • Updated ESS to Vivado 2022.2


  • Bug on missing registers in memory mapped list solved


  • On project open SciCompiler will lock for missing linked files and ask user to provide the new path
  • Lemo on DT5560
  • Updated Caen Lib
  • Bug on data type for variable. Not working with integer (MR !11)
  • Peak finder hdl bug (MR !10)
  • Add custom notes to top page and sub pages (MR !9)
  • Hierarchical Tree for subdesign


  • Log in resource explorer


  • Error in project link for Petiroc components
  • Resource Explorer is protected agaist missing board libraries


  • Add EULA to setup (MR !7)
  • Added log features to license and cloud (MR !6)
  • Added CI/CD automatic upload on the new Sci-Compiler site (MR !5)
  • Shortcut to create registers and port
  • MCA fast
  • Transistor reset processing chain

[2023.03.13.1] - Viareggio Edition

  • (1) Offline compile for X2740-DPP
  • (5) Bug on Resource Explorer list read out more data than available

[2023.02.28.1] - Viareggio Edition

  • (1) New ess DRGO core

[2023.02.10.2] - Viareggio Edition

  • (1) Support for R5560SE
  • (1) Re-target for different hardware
  • (5) Bug on tof spectrum patched, no more dead-time between bins
  • (1) Switched to Sci-SDK library
  • (1) Official Support for remote compile
  • (1) Simulation for all board except DT5550W and V2495

[2022.11.0.3] - Bellagio Edition

  • (5) Simulation, missing dll in setup make unusable the register script editor
  • (1) DT1260 support remote customization service
  • (1) DT5560/R5560-A/R5560-A-SE support remote customization service
  • (1) X274X Dpp mode, Global software RUN enable and disable all DPP output LIST from software
  • (1) X274X Dpp mode, Software enable control each DPP enable signal LIST
  • (1) Support to the new BETA library SciSDK:

[2022.11.0.1] - Bellagio Edition

  • (1) Simulation, for now supported for DT1260 only and in local
  • (5) Solved bug on trigger for frame readout
  • (5) Solved bug on spectrum, the running flag never go back to zero after a start

[2022.9.0.5] - Bellagio Edition

  • (5) Bug in Image Transfer prevent external trigger to be selected from SDK

[2022.9.0.4] - Bellagio Edition

  • (1) Support for V2740 DT2740 V2745 DT2745
  • (1) Cloud compiling feature for X274X boards: see application note (DA SCRIVERE YURI)
  • (1) Migrated on MyCAEN+
  • (1) Support for trial license
  • (1) Support for viewer only mode
  • (1) New license manager with integrated MyCAEN interface for dongle and trial license management
  • (1) Support to the new R5560 architecture with better integration between base and DAQ
  • (1) (R5560/R5560SE) Flag signal connect adjacent DAQ in order to allow fast trigger or synchronization between DAQ
  • (1) Flag signal example to make H-LINK delay deterministic (see AN
  • (5) R5560SE DAQ clock is now provided from the BASE and acquisition of all DAQ are synchronous
  • (1) Removed limit of 64K samples per oscilloscope. Now oscilloscope can use all the available memory
  • (1) User Guide for X2740/5 DPP/Wave readout block
  • (5) Updated DT1260(SCIDK) sdk library. Missing ReadFIFO
  • (5) Bug in the framework of DT1260 read an extra work corrected. At the end of a FIFO readout it causes a missed word in long packet
  • (1) Possibility to install and run SciCompiler even without any locally installed Vivado or Quartus
  • (5) Bug on digitizer IP prevent a correct online data decoding in Resource Explorer with more than 2 channels