Release Version 2023.7.28.1

Changelog

All notable changes to this project will be documented in this file.

[2023.7.28.1]

  • Ask to save on exit

[2023.7.26.1]

  • Hidden I/O not compatible with the selected board. Applied to toolbar and quick menu

[2023.7.25.3]

  • Bug fixed on register compiling. During save, register addresses were reset to 0.
  • Rise time of a signal measurament using R5560 (example)

[2023.7.25.2]

  • Bug in log4net resource explorer

[2023.7.25.1]

  • Better log on License Manager
  • R5560-A dcp missing

[2023.7.24.2]

  • Updated ESS to Vivado 2022.2

[2023.7.24.1]

  • Bug on missing registers in memory mapped list solved

[2023.7.21.1]

  • On project open SciCompiler will lock for missing linked files and ask user to provide the new path
  • Lemo on DT5560
  • Updated Caen Lib
  • Bug on data type for variable. Not working with integer (MR !11)
  • Peak finder hdl bug (MR !10)
  • Add custom notes to top page and sub pages (MR !9)
  • Hierarchical Tree for subdesign

[2023.7.20.1]

  • Log in resource explorer

[2023.7.18.1]

  • Error in project link for Petiroc components
  • Resource Explorer is protected agaist missing board libraries

[2023.7.14.1]

  • Add EULA to setup (MR !7)
  • Added log features to license and cloud (MR !6)
  • Added CI/CD automatic upload on the new Sci-Compiler site https://www.sci-compiler.com (MR !5)
  • Shortcut to create registers and port
  • MCA fast
  • Transistor reset processing chain

[2023.03.13.1] - Viareggio Edition

  • (1) Offline compile for X2740-DPP
  • (5) Bug on Resource Explorer list read out more data than available

[2023.02.28.1] - Viareggio Edition

  • (1) New ess DRGO core

[2023.02.10.2] - Viareggio Edition

  • (1) Support for R5560SE
  • (1) Re-target for different hardware
  • (5) Bug on tof spectrum patched, no more dead-time between bins
  • (1) Switched to Sci-SDK library
  • (1) Official Support for remote compile
  • (1) Simulation for all board except DT5550W and V2495

[2022.11.0.3] - Bellagio Edition

  • (5) Simulation, missing dll in setup make unusable the register script editor
  • (1) DT1260 support remote customization service
  • (1) DT5560/R5560-A/R5560-A-SE support remote customization service
  • (1) X274X Dpp mode, Global software RUN enable and disable all DPP output LIST from software
  • (1) X274X Dpp mode, Software enable control each DPP enable signal LIST
  • (1) Support to the new BETA library SciSDK: https://github.com/NuclearInstruments/SCISDK

[2022.11.0.1] - Bellagio Edition

  • (1) Simulation, for now supported for DT1260 only and in local
  • (5) Solved bug on trigger for frame readout
  • (5) Solved bug on spectrum, the running flag never go back to zero after a start

[2022.9.0.5] - Bellagio Edition

  • (5) Bug in Image Transfer prevent external trigger to be selected from SDK

[2022.9.0.4] - Bellagio Edition

  • (1) Support for V2740 DT2740 V2745 DT2745
  • (1) Cloud compiling feature for X274X boards: see application note (DA SCRIVERE YURI)
  • (1) Migrated my.scicompiler.cloud on MyCAEN+
  • (1) Support for trial license
  • (1) Support for viewer only mode
  • (1) New license manager with integrated MyCAEN interface for dongle and trial license management
  • (1) Support to the new R5560 architecture with better integration between base and DAQ
  • (1) (R5560/R5560SE) Flag signal connect adjacent DAQ in order to allow fast trigger or synchronization between DAQ
  • (1) Flag signal example to make H-LINK delay deterministic (see AN https://www.nuclearinstruments.eu/an-008-r5560-se-daqs-horizontal-interconnection/)
  • (5) R5560SE DAQ clock is now provided from the BASE and acquisition of all DAQ are synchronous
  • (1) Removed limit of 64K samples per oscilloscope. Now oscilloscope can use all the available memory
  • (1) User Guide for X2740/5 DPP/Wave readout block
  • (5) Updated DT1260(SCIDK) sdk library. Missing ReadFIFO
  • (5) Bug in the framework of DT1260 read an extra work corrected. At the end of a FIFO readout it causes a missed word in long packet
  • (1) Possibility to install and run SciCompiler even without any locally installed Vivado or Quartus
  • (5) Bug on digitizer IP prevent a correct online data decoding in Resource Explorer with more than 2 channels